Thermal Oxide Wafer: 300 nm SiO2 Layer on Si (100), 4"dia x 0.5 mm t, P type, 2SP, R:1-10 ohm-cm - Fm300SOonSIBa100D0525C2R1US Pouch Cell Polishing: one-side side polishd (

Polishing:            one-side side polishd ( back side etched )

Pocket Size(mil):   L105*W110*D28      Pocket Size(mm):  L2

Dimension:  100x100 x 3

Non REO Impurity <0

100 pcs of spacer made of 304 Stainless for CR20 Series Coin cell

Thermal Oxide Wafer: 300 nm SiO2 Layer on Si (100), 4"dia x 0.5 mm t, P type, 2SP, R:1-10 ohm-cm - Fm300SOonSIBa100D0525C2R1US Pouch Cell Polishing: one-side side polishd (Thermal oxide SiO2 layer on 4" Silicon wafer Oxide layer thickness: 300 nm ( 3000A) + 10% Refractive index 1. 455 Silicon Wafer Specifications: Conductive type: P type B dped Resistivity: 1 10 ohm. cm (If you would like to measure the resistivity accurately, please order our Portable 4 Probe Resistivity Testing Instrument.) Size: 4" + 0. 5 mm x 0. 5 mm Orientation: (100) + 1o Polish: Two sides polished Surface roughness, Ra: < 5A (RMS) Related